1. Field of the Invention
The present invention relates to the field of communication between interconnected modules.
2. Description of the Relevant Art
In the field of computing, conventional systems are centred around a specialized bus which interconnects several agents. Here, “agent” is understood to mean an element able to receive or to dispatch data over a bus, for example a central processing unit, a memory, an input/output device, etc.
According to a specific protocol individual to the bus, only one agent can dispatch a message over the bus simultaneously. The execution of a processing requires that operands be present in the agent that will execute the processing and consequently demand the transfer of data between agents via the communication system. Here, “operand” is understood to mean an element to which an operation pertains.
For example, a system including an arithmetic coprocessor and a memory of SDRAM type which contains data must, in order for it to be possible for an operation to be executed, transfer the operands stored in the memory by way of the controller of the memory, then by way of the bus to the coprocessor. The results of the operation will be transferred over the same bus.
This results in the number of exchanges being limited due to the use of a bus which forms a single and bounded communication resource, the bandwidth of the communication system formed by the bus being finite.
In applications where high performance is necessary, the execution of a programme requires a specific organization of the instructions so as to optimize and best sequence the various exchanges between the agents that are connected to the communication bus, so as to optimize the use of the bandwidth. The compilers may take charge of this type of problem, but in a non-optimal manner and under the proviso that a part of the resources of the system is used for the management of these exchanges. The system thus loses efficiency and the performance degrades all the more quickly the higher the number of agents that are present on the communication bus.
Moreover, it is possible to interconnect two distinct buses, for example of PCI type, by means of a bridge allowing data transfer from one bus to another. Such an architecture is known through the document <http://www.hitachi-ul.co.jp/PROP/IP/epharaohip.html>. A difficulty then arises in the case of an error in transferring data, for example to an address that does not exist in the other bus. Current techniques do not make it possible to manage situations of this kind satisfactorily.